Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet Applications to Achieve Compliance and High-Speed Connectivity

Tewksbury, Massachusetts--(Newsfile Corp. - June 21, 2022) - Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications.

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Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential back tracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information is available at www.avery-design.com.

Contacts:

Christopher Browy
(978) 851-3627
cbrowy@avery-design.com

Mike Sottak
6502489597
mike@wiredislandpr.com

Source: Avery Design Systems

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