Astera Labs and Avery Design Partner on CXL(TM) 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications

Tewksbury, Massachusetts--(Newsfile Corp. - April 28, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions for intelligent systems, successfully used Avery's Compute Express Link (CXL) 2.0 and PCI Express® (PCIe®) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio.

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Key Takeaways:

• Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems
• Avery PCIe and CXL Verification IP enabled Astera Labs to get to market faster

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About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

Contacts:
Mike Sottak
6502489597
mike@wiredislandpr.com
Source: Avery Design Systems

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