Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard

Tewksbury, Massachusetts--(Newsfile Corp. - December 8, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new HBM3 interface standard. Rambus uses Avery's high-quality HBM3 memory models to verify the new Rambus HBM3 Memory Subsystem.

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Key Takeaways:

• Rambus uses Avery's high-quality, full-featured memory model to verify its HBM3 PHY and controller.
• Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP.
• Customers can then license the Avery memory models for use in full SoC verification.

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About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

Contacts:

Mike Sottak
6502489597
mike@wiredislandpr.com

Source: Avery Design Systems

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