Axiomise

RISC-V International provides an open-source architecture which anyone can use to build a custom RISC-V core or SoC. How do we verify beyond doubt that there are no bugs? Axiomise formalISA app can find bugs as well as build proofs of bug absence, so no more costly respins! Verify beyond doubt using automated formal verification for in-order cores as well as out-of-order cores, catching functional, safety, security and low-power related issues. #processor #formalverification #icdesign #riscv #power #performance #area #safetyverification #securityverification #soc https://lnkd.in/e_KiMC5t

Axiomise is delighted that two established leaders in their own field decided to join our technical advisory board. Both Colin McKellar and Vidya Chandran Darbari are reputed leaders with years of experience building and running multi-disciplinary teams and being at the top end of the game. Together with the executive team at Axiomise, they will shape our journey in making formal normal. #formalverification #leaders https://lnkd.in/eUSYU8fk

Most in industry approach us with help on projects to verify their complex designs using #formalverification. While we continue to enjoy proving bug absence, we have never lost sight of education!📚 💯The primer video has reached 100K views on our channel. 🔔There is a ton of content on our channel on formal, if you haven’t looked at it yet, check it out and subscribe! 🔗Formal verification: A quick primer https://lnkd.in/eDaNUba

Bernard Murphy describes an enduring growth challenge for #formalverification in this new piece. “Formal methods are the ideal way to prove correctness in such cases, assuming an appropriate level of finesse in proofs. Axiomise use their formalISA app to run push-button proofs on correctness on 32-bit and 64-bit implementations, and they have production-ready implementations for RV32IMC and RV64IMC instruction sets. Examples of problems found include a bug in RISC-V specification v 2.2 and over 70 deadlocks found in the previously verified zeroriscy. The app found new bugs in the ibex core and architectural issues with LOAD instruction in zeroriscy. It found 30 bugs in WARP-V (2-stage, 4-stage, and 6-stage in-order cores) and cv32e40p core from OpenHW. Axiomise has also verified the out-of-order execution CVA6 core using formalISA. Details of these bugs are available on GitHub”. https://lnkd.in/eBS4NzA9

Ashish Darbari Ziyad Hanna Manish Pandey Dirk Seynhaeve Jim Henson Simon Davidmann sat with Ann Mutschler and Adam Kovac for a roundtable to discuss some of the issues about finding and fixing bugs in the ICs. Ashish Darbari described the problems and solutions from a #formalverification point of view and said " Information drafting (specifications) and sharing that information are two key elements of any verification task that relies on requirements. In formal verification, the gap between specifications and implementation verification is thrown wide open very early in the verification phase, as formal is brittle. With an almost infinite stream of stimulus coming into the DUT, a lot of which can be an illegal stimulus, our reliance on well-crafted specifications is ever so important. The problem is that, for a lot of functional verification of micro-architecture, we rely on micro-architecture specification documents. But it is not easy to describe the side-band information. Consider, for example, verifying a command processor in a GPU or an AI chip with formal end-to-end. We expect to know the behavior of every top-level pin of the processor, and there may be a few hundred of them. Typically, these are driven via the GPU sub-system or firmware/drivers or software, and the processor is verified in-situ in emulation. How on earth can a designer know the end-to-end behavior of every pin of the command processor we are verifying with formal? We work with design teams to help them develop this information, and then use this in formal and validate it in simulation and emulation. In general, however, this is not a solved problem, and it can only be made better if verification teams have an audience of architects, designers, firmware, and software teams, where everyone collectively agrees on the interface contracts between software and hardware, and within hardware. One thing we often see in formal verification-based work is the treatment of exceptions and error handling, which is often not well specified or understood, and there is often a wide gap between software and hardware teams. We often hit upon these very early in the project, and upon debug the schisms are well exposed. Then we try to bring the teams together, get clarity, refine the specification via assertion/cover, and then prove that it matches with the implementation. In addition, there is another feature of this information structure that is important to highlight — configuration-dependent design behavior. There are too many configurations to be tested, and clearly scoping out which ones are important and urgent is the key to identifying bugs and addressing time-to-market." https://lnkd.in/dXQ_y9Pt

How do you deal with uncertainty dealing with AI/ML? In this excellent piece by Karen Heyman from Semiconductor Engineering, she captures interesting insights from several experts who don't always agree! Ashish Darbari CEO of Axiomise, disagrees with the premise that no one knows how the models are implemented. He said “It is more the case that the model’s details are not visible. There is a difference between the two artifacts. My sense is that even if we don’t know what exact model has been implemented, we could still test that model against a design model. In the case of semiconductors, the problem is less severe than the software-as-domain specialists, such as architects, designers and verification engineers, all of whom tend to know what to expect from the design model. This means extensive testing of the design against a black box AI model would reveal acceptable and unacceptable patterns across the I/O, which will make it easier to establish trust in the AI-generated black box model. Coverage models can be developed independently to validate the quality of the black box model. Again, the guide would be a coverage specification obtained from domain experts — designers and architects. Another way to address the black box models is to bring in symbolic AI to build alternative models, which are better in that one can explain these, gain deeper insights, and use these explainable AI models to compare and equivalence check against the black box models to authenticate their validity and completeness. This will allow the developers of black box models to have perhaps more optimized implementations and not reveal the secret sauce, but still get validated against what is open to investigation, such as an explainable AI model.” Other experts who provided insights include Neil Hand, Frank Schirrmeister Steve Roddy Patrick Donnelly. Siemens EDA (Siemens Digital Industries Software) Quadric Arteris Expedera Inc. https://lnkd.in/gn9FPH7g #ai #machinelearning #eda #semiconductors #verification #validation #formalverification #uvm #icdesign

Great article by Ann Mutschler from Semiconductor Engineering with incredible insights from several top global experts on how multi-die design is pushing complexity to the max from design and verification to packaging. “Everything was clock speed and performance in the good old days of IBM mainframes and Intel/AMD x86 servers,” observed Ashish Darbari, CEO of Axiomise. Thanks to the Arm architecture, from the late ’90s onward, power became the dominant push in the industry, and with chips being squeezed into smaller form factors such as mobile phones and watches and miniaturized sensors, performance along with power and area (PPA) determined the quotient of design complexity. 72% of ASICs are reported to manage power actively, and power management verification is a growing challenge, as reported by the Wilson Research report from 2022. However, with the rapid adoption of silicon in automotive and IoT, functional safety and security dominate the design complexity. You cannot design a chip without thinking of PPA — and one or both, safety and security. Test and verification have evolved from the days of architectural verification suites of the ’70s and ’80s to constrained random, formal verification, and emulation. Each of the new verification technologies copes with different abstraction levels of designs and, if used correctly, can be complementary. Whereas emulation can reason about functionality and performance at the full-chip level, constrained random and formal are great technologies at the RTL level, with formal being the only technology to build proofs of bug absence. We see an increase in the use of formal verification for architectural verification, as well as in finding deadlocks, livelocks and logic-related bugs.”  #3dic #multidie #semiconductors #eda #design #verification https://lnkd.in/g8B8Kb2v

What a wonderful day the team had, celebrating 🌹St. George’s Day 🌹organised by the St Albans District Chamber of Commerce on Friday! It was great opportunity to meet new people, and see the great work that is happening in the community! Many thanks to Pat Strods and the chamber’s team👏👏👏 Ben Hanlin 🧙 was terrific, and made the day very magical indeed.

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? ▶ Find out why and how #formalverification can help in this new piece by Ashish Darbari. https://lnkd.in/dSE_Qk4u

🤔Did you know that between March and April, nearly 9500 listeners tuned in to the EE Times | Electronic Engineering Times Embedded Edge with Nitin Dahad and our Founder and CEO Ashish Darbari? Find out how we are making formal normal❤️ ➡️ https://lnkd.in/d7KqVYAz #formalverification #loveformal #icdesign #verification #validation #semiconductors